This application is based on Japanese patent application HEI 9-352434 filed on Dec. 5, 1997, the whole contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a multi-layer wiring structure of integrated circuit suitable for LSI and the like and a method of forming a multi-layer wiring.
b) Description of the Related Art
Conventionally, a multi-layer wiring structure such as shown in FIG. 23 is known.
On the surface of a semiconductor substrate 1 made of silicon or the like, an insulating film 2 made of silicon oxide or the like is formed. A contact hole 2a is formed through the insulating film 2 in the area corresponding to a connection area 1a (e.g., impurity doped region) in the surface layer of the substrate. A first wiring layer 3 is formed on the insulating film and connected via the contact hole 2a to the connection area 1a of the substrate surface.
On the insulating film 2, an interlayer insulating film made of phosphosilicate glass (PSG) or the like is formed covering the wiring layer 3. A contact hole 4a is formed through the insulating film 4 in an area corresponding to a partial area of the wiring layer 3. On the insulating film 4, a second wiring layer 5 is formed, while being connected via the contact hole 4a to the wiring layer 3.
As an example of the wiring layer 3, a lamination structure is known (e.g., refer to U.S. Pat. No. 5,070,036). This lamination structure is made of, as shown in FIG. 24, a Ti layer 3a of 2 to 10 nm in thickness, a TiN or TiOxNy (x=0.05 to 0.2, y=0.95 to 0.8) layer 3b of 50 to 200 nm in thickness, a Ti layer 3c of 7 to 20 nm in thickness, an Al alloy (Alxe2x80x94Sixe2x80x94Ti, or the like) layer 3d of 300 to 1000 nm in thickness, a Ti layer 3e of 7 to 20 nm in thickness, and a TiOxNy (x=0.1 to 0.3, y=0.9 to 0.7) layer 3f of 50 to 500 nm in thickness, respectively stacked in this order from the bottom.
As another example of the wiring layer 3, a lamination structure is known (e.g., refer to JP-A-HEI-5-190551). This lamination structure is made of, as shown in FIG. 26, a TiN layer 3A, an Al alloy (or Al) layer 3B, a Ti layer 3C, and a TiN layer 3D, respectively stacked in this order from the bottom.
According to the conventional technique shown in FIG. 24, while the TiON layer 3f is formed on the Ti layer 3e through sputtering, the surface of the Ti layer 3e is oxidized and a TiOx film 3g having a high resistivity is formed as shown in FIG. 25. Since this layer having a high resistivity is interposed between the Ti layer 3e and TiON layer 3f, the resistance (via resistance) of the interlayer contact area between the wiring layers 3 and 5 increases by about 20%.
According to the conventional technique shown in FIG. 26, since the TiN layer 3D is formed on the Ti layer 3C, the surface of the Ti layer 3C is free from oxidation. However, according to the studies made by the inventor, it has been found that the resistance (via resistance) of the interlayer contact area increases if a plug embedded type wiring layer is formed as the wiring layer 5.
FIG. 27 shows an example of a conventional multi-layer wiring structure. Like elements to those shown in FIGS. 23 and 26 are represented by using identical reference numerals and the detailed description thereof is omitted. On an insulating film 2, a lamination structure is formed which is made of a Ti layer 3E of 10 to 20 nm in thickness, a TiN layer 3A of 100 nm in thickness, an Al alloy (Alxe2x80x94Sixe2x80x94Cu) layer 3B of 350 nm in thickness, a Ti layer 3C of 10 nm in thickness, and a TiN layer 3D of 50 nm in thickness, sequentially stacked in this order from the bottom. A lamination of the Ti layer 3E/TiN layer 3A under the Al alloy layer 3B constitutes a tight adhesion layer for the Al alloy layer 3B, and a lamination of the TiN layer 3D/Ti layer 3C functions as a protective layer for the Al alloy layer 3B. The lamination wiring structure is patterned in a desired wiring pattern to form a wiring layer 3.
On the insulating film 2, an insulating film 4 is formed covering the wiring layer 3. A contact hole 4a is formed through the insulating film 4 by selective dry etching. During this selective dry etching, pin holes P may be formed through the lamination of the Ti layer 3C /TiN layer 3D. Next, a tight adhesion layer 6 is formed covering the inner surface of the contact hole 4a and the upper surface of the insulating film 4. As the tight adhesion layer 6, a lamination of a Ti layer and a TiN layer stacked upon the Ti layer is used. The coverage of the tight adhesion layer 6 lowers at the areas where the pin holes P are formed.
Next, a W layer is formed over the substrate through blanket chemical vapor deposition (CVD). Thereafter, the W layer is etched back to leave a plug 7 made of W in the contact hole 4a. Blanket CVD generally uses WF6 as a source gas. Therefore, WF6 reaches the Al alloy layer 3B via the coverage lowered areas of the pin holes P and forms a high resistance aluminum fluoride (AlFx) layer 8 by the following chemical formula.
WF6+Alxe2x86x92AlFx+W 
Thereafter, a wiring material layer made of Al alloy or the like is formed over the substrate. By pattering the lamination of the wiring material layer and tight adhesion layer 6, a second wiring layer connected to the plug 7 is formed. Since the high resistance AlFx layer 8 exists at the interlayer contact area between the second wiring layer and the wiring layer 3, the via resistance increases. An increase of the via resistance changes with the conditions of the generated AlFx layer 8, and the via resistance distributes in a range from a two- to threefold to a tenfold of a standard via resistance or further larger.
It is an object of the present invention to provide a novel multi-layer wiring structure or wiring layer forming method capable of suppressing a resistance increase in the interlayer contact area.
According to one aspect of the present invention, a multilayer wiring forming method comprises the steps of:
forming an Al or Al alloy layer on a first insulating film covering a substrate;
forming a first Ti layer on the Al or Al alloy layer;
sequentially laminating a first TiN layer and a first TiON layer in this order on the first Ti layer through reactive sputtering;
patterning a lamination of the Al or Al alloy layer, the first Ti layer, the first TiN layer, and the first TiON layer into a desired wiring pattern to form a first wiring layer;
forming a second insulating film on the first insulating film, the second insulating film covering the first wiring layer;
forming a contact hole through the second insulating film, the contact hole reaching a partial surface area of the first TiON layer;
forming a tight adhesion layer covering an inner surface of the contact hole;
forming a conductive plug embedding an inside of the contact hole, with the tight adhesion layer being interposed under the conductive plug; and
forming a second wiring layer on the second insulating film, the second wiring layer being connected to the plug.
With the resulting structure, the first wiring layer is a lamination of the Al or Al alloy layer, first Ti layer, first TiN layer, and first TiON layer. The Al or Al alloy layer is a main wiring layer of the first wiring layer. The first Ti layer prevents the surface of the Al or Al alloy layer from being nitrided while the first TiN layer is formed. The first TiN layer prevents the surface of the first Ti layer from being oxidized while the first TiON layer is formed. The first TiON layer functions as an antireflection layer during a photolithography process for patterning the first wiring layer and also prevents generation of pin holes during a dry etching process for forming the contact hole in the second insulating film.
A nitride film is therefore hard to be formed on the surface of the Al or Al alloy layer, and an oxide film is also hard to be formed on the surface of the first Ti layer. Since pin holes are not formed in the first TiON layer during the dry etching process for forming the contact hole, the coverage of the tight adhesion layer does not lower, and an AlFx layer is suppressed from being formed through reaction between WF6 and Al while the plug is formed. Accordingly, a via resistance in the interlayer contact area between the first and second wiring layers can be prevented from being increased.
In this multi-layer wiring structure, a tight adhesion layer for the higher level wiring layer may be a lamination of a second Ti layer, a second TiN layer, a second TiON layer, and a third TiN layer stacked one on top of the other in the order stated. In this case, the second Ti layer functions as a layer which lowers resistance. The second TiN layer prevents the surface of the second Ti layer from being oxidized while the second TiON layer is formed. The second TiON layer functions as a barrier layer for preventing permeation of WF6 while a plug is formed. The third TiN layer improves tight adhesion to the W layer and prevents diffusion of oxygen from the second TiON layer to the W layer.
Since permeation of WF6 is intercepted by the second TiON layer, reaction between WF6 and Al does not occur so that a resistance rise in the interlayer contact area can be suppressed. Since the third TiN layer intercepts diffusion of oxygen from the second TiON layer to the W layer, it is possible to prevent an etching rate of the W layer from being locally raised, so that the W layer can be etched back uniformly.
Stable and good electrical connection is achieved by sequentially laminating Ti/TiN/TiON/TiN (lower layer/upper layer) and using this lamination as a tight adhesion layer between an Si substrate and a wiring layer to be connected via a contact hole.
Also with respect to electrical connection in a multi-layer wiring structure between a lower level Al wiring layer and a higher level Al wiring layer via a via hole, a resistance increase in an interlayer contact area can be suppressed by using a lamination of Ti/TiN/TiON/TiN as a tight adhesion layer. The via resistance increase can be suppressed more if such a tight adhesion layer is used in combination with a Ti/TiN/TiON/TiN antireflection film.
As above, in the multi-layer wiring structure/for integrated circuits, the uppermost layer of a lower level wiring layer is made of TiON so that pin holes are not formed during a dry etching process for forming a contact hole through an interlayer insulating film. Accordingly, an AlFx layer is not formed in the lower level wiring layer while the plug is formed in the contact hole, and a resistance increase in the interlayer contact area can be suppressed.
A lamination of Ti/TiN/TiON/TiN sequentially stacked is used as the tight adhesion layer. Since the TiON layer intercepts permeation of WF6, reaction between WF6 and Al does not occur. Therefore, a resistance increase in the interlayer contact area can be suppressed. Since the TiN layer covering the TiON layer prevents oxygen diffusion from the TiON layer to the W layer, the W layer can be etched back uniformly.
In a multi-layer wiring structure, in forming an antireflection layer on an Al or Al alloy layer, after the Ti layer is formed, the TiN layer and TiON layer are formed in succession through reactive sputtering. Also, in forming a tight adhesion layer, after the Ti layer is formed, the TiN layer, TiON layer, and TiN layer are formed in succession through reactive sputtering. This successive film forming improves a throughput.